The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device, referred to compilation, starts with an extraction phase, followed by a logic synthesis phase, a fitting phase, and an assembly phase. The extraction phase takes a user design, typically expressed as a netlist in a hardware description language such as Verilog or VHDL, and produces a set of logic gates implementing the user design. In the logic synthesis phase, the set of logic gates is permutated over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device. The clustering, placement, and routing phases assign the various portions of the user design to specific logic cells and functional blocks and determine the configuration of the configurable switching circuit used to route signals between these logic cells and functional blocks, taking care to satisfy the user timing constraints as much as possible. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design.
To improve the performance of a user design implemented on a programmable device, additional optimization phases can be used to optimize the user design. For example, optimization phases can improve the maximum operating speed of the user design or decrease the amount of power required by the user design. One type of optimization phase duplicates portions of the user design in different sections of the programmable device. This type of optimization phase, referred to as logic duplication, uses the duplicate portions of the user design to minimize the signal delay on timing critical paths in the user design, thereby increasing the maximum operating speed of the user design.
Typically, a substantial portion of the signal delay in a user design is determined by the locations of the various portions of the user design on the programmable device. These locations are typically determined during the placement phase of the compilation of the user design. Some prior logic duplication phases are applied to the user design before the placement phase and thus before the locations of the portions of the user design and their associated signal delays have been determined. Because these types of logic duplication phases lack accurate signal delay information, they must essentially guess at the optimal use of the duplicate portions of the user design. As a result, user design performance is rarely optimal.
Conversely, other prior logic duplication phases are applied to the user design after the placement phase. Although these types of logic duplication phases have placement information and thus can estimate signal delay more accurately, the locations of the duplicate portions of the user design have already been fixed; thus the duplicate portions of the user design are often underutilized because they provide little or no reduction in signal delay.
It is therefore desirable for a system and method to improve the effectiveness of logic duplication optimizations. It is further desirable to dynamically allocate the usage of logic duplicates in the user design to maximize the utilization of logic duplicates. It is also desirable to utilize logic duplication optimizations in one or more phases of compilation. It is desirable to apply logic duplication optimizations to a user design to reduce signal delays, improve the routing of connections, and/or decrease power requirements.